1. Field of the Invention
The present invention relates to a power device package, and more particularly, to a power device package including a printed circuit board.
2. Description of the Related Art
Recent developments in power electronics including such devices as servo drivers, inverters, power regulators, and converters are leading to increasing demands for light, small power devices with excellent performance characteristics. Therefore, research is being actively conducted into smart or intelligent power modules in which a variety of power semiconductor chips and low power semiconductor chips, such as IC chips for controlling the power semiconductor chips, can be integrated into one package.
A power device package includes at least one power control semiconductor chip mounted on a substrate and, if necessary, a low power semiconductor chip controlling the power control semiconductor chip. An interconnection pattern is formed on the substrate for connections to the power control semiconductor chip and/or a low power semiconductor chip. The interconnection pattern may be multi-stacked metal layers. For example, the multi-stacked metal layer may have a copper layer formed on the substrate, and a nickel layer covering the copper layer. Since the copper layer has excellent electrical conductivity and the nickel layer has a good anti-oxidation property for the underlying copper layer, the multiple stack structure of the nickel layer and the copper layer may be advantageously used for the interconnection pattern.
The power control semiconductor chip is a large chip requiring a high operating current, while the low power semiconductor chip is a relatively small chip compared to the power control semiconductor chip and does not require a high operating current. Considering the different features between the power control semiconductor chip and the low power semiconductor chip, our inventors envisaged that the power control semiconductor chip might be electrically connected to the interconnection pattern by a heavy wire and the low power semiconductor chip might be electrically connected to the interconnection pattern by a small wire.
But we found that even when a surface oxidation layer is formed on the nickel layer or the copper layer, the heavy wire connected to the power control semiconductor chip could ensure reliable electrical contact with the nickel layer or the copper layer by mechanically passing through the surface oxidation layer, however, the small wire connected to the low power semiconductor chip failed to ensure reliable electrical contact with only the nickel layer or the copper layer. In particular, when a gold wire was used as the small wire, it was difficult to achieve reliable bonding of the gold wire with the interconnection pattern because of the surface oxidation layer formed on the nickel layer or the copper layer.